Non-volatile memory related technologies have been described in U.S. Pat. Nos. 5,600,166 and 6,413,820.
Conventionally, non-volatile memory devices are classified as either a floating gate device or a silicon oxide-nitride-oxide silicon (SONOS) device.
FIG. 1 is a cross sectional view illustrating a conventional floating gate device structure. FIG. 2 is a cross sectional view illustrating a conventional SONOS device structure.
The floating gate device shown in FIG. 1 includes a silicon substrate 10 having a source 11 and a drain 12, a tunnel oxide layer 13, a polysilicon floating gate 14, an oxide-nitride-oxide (ONO) layer 15, and a control gate 16 sequentially formed on the silicon substrate 10 between the source 11 and the drain 12.
In this type of the floating gate device, the voltage of the memory cell is set to a first level by capturing electrons within an electric charge well using a hot carrier injection technique during a programming operation, and the voltage of the memory cell is set to a second, lower level by releasing the electrons blocked in the electric charge well out to a P-type silicon substrate using a direct tunneling or F-N tunneling technique during an erasing operation.
The floating gate device has a fast programming speed, superior retention characteristics, and a wide threshold voltage (Vt) window. As a result, it has been used for most conventional non-volatile memories.
However, such a floating gate device is disadvantageous in that the fabrication process of the floating gate is very complicated, and particularly, exhibits scaling limits due to high electric charge loss caused by coupling between adjacent memory cells.
On the other hand, the conventional SNOS device shown in FIG. 2 includes a P-type silicon substrate 20 having a source 21 and a drain 22, an ONO layer 23 formed by sequentially depositing a tunnel oxide layer, a trap nitride layer, and a block oxide layer on the substrate 20, and a gate 24 formed on the ONO layer 23.
In such a SONOS device, the voltage of the memory cell is set at a first level by trapping electrons in a trap site which exists in the trap nitride of the ONO layer 23 using the direct tunneling or F-N tunneling technique during the programming operation, and the voltage of the memory cell is set at a second, lower level by tunneling the electrons out of the trap site to the P-type substrate using the F-N tunneling, the direct tunneling, or the trap assisted tunneling technique during the erasing operation.
The SONOS device can be scaled as in the logic device, can be fabricated in simple fabrication, and has a high immunity against local defects and cosmic rays. However, the SONOS device has a bad retention characteristic, a slow programming speed, and a narrow threshold voltage window in comparison with the floating gate device.